Cadence

SPB

OrCAD

16.60.011 Hotfix | 564.0 mb

Cadence Design Systems, Inc. announce hotfix version 011 for 16.60 release. This update includes some critical bug fixes. Cadence Design Systems, Inc., a leader in global electronic design innovation, launched the Cadence OrCAD 16.6 design solution with new features, enhanced customization capabilities, and 20 percent simulation performance improvements that provide customers a shorter, more predictable path to product creation.

This latest release offers numerous improvements to tool usability and performance, but at the heart of 16.6 are three key benefits: enhanced miniaturization capabilities, timing-aware physical implementation and verification for faster timing closure, and the industry’s first electrical CAD team collaboration environment for PCB design using Microsoft SharePoint technology.

DATE: 06-14-2013 HOTFIX VERSION: 011

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CCRID PRODUCT PRODUCTLEVEL2 TITLE

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982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf

1055338 SIP_LAYOUT DRC_CONSTRAINTS Soldermask to Via drcs on bondfingers

1093375 ALLEGRO_EDITOR PLACEMENT Align Module with Zero spacing value space the modules further away the modules should be nearer

1103201 RF_PCB FE_IFF_IMPORT Wrong permissions to map file during IFF import

1106900 CONCEPT_HDL COMP_BROWSER Component Browser performance utility should honor CPM directives for include and exclude PPT

1110178 ALLEGRO_EDITOR EDIT_ETCH Line Width Retention should be controlled via setting

1110323 APD DXF_IF DXF out is offsetting square discrete pads.

1123581 ALLEGRO_EDITOR MANUFACT Dimension Line gets changed on board

1134083 CONCEPT_HDL OTHER Published PDF file's hyperlinks do not work fine when user use double digits partitions for page Border.

1139338 ALLEGRO_EDITOR DRC_CONSTR The total etch length does not seem to work for Xnets after setting the variable "retain_electrical_constraints_on_nets"

1139361 ALLEGRO_EDITOR DRAFTING Angular dimension tolerance is incorrect when plus minus tolerances are equal.

1141882 ALLEGRO_EDITOR EDIT_ETCH Allegro Crashes during diffpair slide

1142876 ALLEGRO_EDITOR SHAPE No DRC error when airgap between place bounds exactly zero

1145235 CONCEPT_HDL CONSTRAINT_MGR DEHDL CM gives error when trying to launch SigXP

1145243 ALLEGRO_EDITOR NC Duplicate drills found in the NC Drill output

1145260 SIP_LAYOUT DIE_EDITOR Enable "Copy" in die editor

1145284 CONCEPT_HDL CORE Publish PDF crashes DE HDL

1145333 ALLEGRO_EDITOR SHAPE SHAPE boundary may not cross itself. Error cannot be fixed.

1145856 ALLEGRO_EDITOR DRC_CONSTR DRC Line to Thru Pin appear while Fillet be added

1146287 PCB_LIBRARIAN CORE PDV expand pins and change origin sets coordinates for few pins wrong and places pins on top of each other after collaps

1146865 ALLEGRO_EDITOR DATABASE Allegro crashes when trying to place mechanical symbol

1148513 ALLEGRO_EDITOR OTHER Importing a subdrawing file causes incorrect net name assignment.

1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF

1149025 ALLEGRO_EDITOR INTERFACES IPC-2581 imports cross-hatched shapes as solid

1149948 APD OTHER Stream_out hangs on this design -- hang processing merge of overlapping shapes using poly_deletecolinear_only()

1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes

1151450 SIP_LAYOUT DXF_IF DXF export from CDNSIP missing symbols

A hot fix is a software maintenance package containing a small number of code fixes, designed to fix a small number of critical problems. A hot fix enables a customer to receive fixes for urgent problems, without having to wait for the next service pack.

Each successive Fix Pack is comprehensive and contains the material from the earlier Fix Packs for that Release, as well as all Interim Fixes made available since the previous Fix Pack or full Release. In other words, when multiple Fix Packs are available, you would not need to apply Fix Pack 1 before applying Fix Pack 2.

About Cadence Design Systems, Inc.

Cadence enables global electronic design innovation and plays an essential role in the creation of today's integrated circuits and electronics. Customers use Cadence software, hardware, IP, and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers, and research facilities around the world to serve the global electronics industry.

Name:

Cadence SPB OrCAD

Version:

(32bit) 16.60.011 Hotfix

Home:

www.cadence.com

Interface:

english

OS:

Windows XP / Vista / Seven

System Requirements:

Cadence SPB OrCAD 16.60.000 - 16.60.010

Size:

564.0 mb

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