Cadence

SPB

OrCAD

的16.60 012和16.50 045升级补丁。

16.50 045更新范围：

DATE: HOTFIX VERSION: 012

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CCRID PRODUCT PRODUCTLEVEL2 TITLE

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914562 ALLEGRO_EDITOR GRAPHICS 3D viewer, PCB Symbol view in DRA needs to be same as in BRD

1120397 CONCEPT_HDL CREFER CreferHDL attempts to create missing vlog004u.sir files

1136449 ALLEGRO_EDITOR GRAPHICS about previous shape fill display

1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.

1150334 ALLEGRO_EDITOR EDIT_ETCH AiDT deletes the clines and turns it back to PLAN line

1151100 APD VIA_STRUCTURE Net filter not working in replace via structure command.

1151126 APD VIA_STRUCTURE Getting "group is not appropriate at this time" message when using Temp Group.

1151458 GRE CORE GRE crashes on Plan Spatial

1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy

1152151 ALLEGRO_EDITOR INTERFACES dxf2a gives error [SPMHGE-268]1152475 PSPICE SIMULATOR RPC server unavailable error while simulating the attached design

1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger

1153006 ALLEGRO_EDITOR SKILL axlUIWPrint dose no work correctly in allegro PCB Editor 16.6.

1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places

1153461 SIP_LAYOUT DIE_EDITOR Regression problem in 16.6 ISR: Dia Abstract ECO is causing Die Editor Finish to fail

1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.

1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer

16.60 012更新范围：

DATE: 06-28-2013 HOTFIX VERSION: 045

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CCRID PRODUCT PRODUCTLEVEL2 TITLE

=====================================================

982306 CONCEPT_HDL OTHER When plotting a PDF publisher output the page coming out half inch bigger in pdf

1145635 ALLEGRO_EDITOR SHAPE Auto Voding on the same net shapes with other parameter.

1148734 CONCEPT_HDL OTHER Logical Symbol Text is turned upside down after extracting PDF by Publish PDF

1150274 CONCEPT_HDL CORE Uprev from 16.3 to 16.6 is not preserving RefDes

1151932 F2B PACKAGERXL PXL error when case is wrong at differen levels in hierarchy

1152206 CONCEPT_HDL CORE ROOM Property value changes when saving another Page

1152737 ALLEGRO_EDITOR SKILL dbids are removed because highlighted objects in setting the xprobe trigger

1153279 CONSTRAINT_MGR OTHER Netrev changing design accuracy from 3 to 2 dec places

1154185 SIG_INTEGRITY SIGNOISE Signoise didn't do the Rise edge time adjustment.

1154973 APD EDIT_ETCH Same Net "Line to Line" violation occurs even with "Allow DRC's" turned off.

1155227 ALLEGRO_EDITOR DRC_CONSTR via to shape check on the negative layer

1155951 ALLEGRO_EDITOR DRAFTING Allegro crashes when placing part in the design.

Cadence SPB OrCAD 16.50(60).045(012) Hotfixes | 1.2 Gb

Cadence Design Systems, Inc. announce hotfixes version 012 for 16.60 release and version 045 for 16.50. This update includes some critical bug fixes.

Name:

Cadence SPB OrCAD

Version:

(32bit) 16.50(60).045(012) Hotfixes

Home:

www.cadence.com

Interface:

english

OS:

Windows XP / Vista / Seven

System Requirements:

Cadence SPB OrCAD 16.60.000 - 16.60.011 / Cadence SPB OrCAD 16.50.000 - 16.50.044

Size:

1.2 Gb

Special Thanks 0mBrE

Download filefactory

http://www.filefactory.com/file/4xck64lgp4f1/n/cspor1650045ho.rar

http://www.filefactory.com/file/4lwhdb0gqs6h/n/cspor1660012ho.rar