Learn to build OVM & UVM Testbenches from scratch

6 Hours | Video: AVC (.MP4) 1280x720 30fps | Audio: AAC 44.1KHz 2ch | 745 MB

Genre: eLearning | Language: English

Learn and Start building Verification Testbenches in SystemVerilog based Verification Methodologies - OVM and UVM

* Lectures 36

The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.

*Basic concepts of two (similar) methodologies - OVM and UVM -

* Coding and building actual testbenches based on UVM from grounds up.

* Plenty of examples along with assignments (all examples uses UVM)

* Quizzes and Discussion forums

* Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol - APB Bus