Vivado Design Suite是Xilinx为HDL设计的综合和分析而设计的软件套件，取代了Xilinx ISE，具有用于片上系统和高级综合的附加功能。
Vivado代表了对整个设计流程的重新思考和重新思考，并且被评论者描述为“精心构思，紧密集成，快速，可扩展，可维护和直观”。
Vivado Design Suite 2019.1，其支持：量产器件航天级 Kintex UltraScale：- XQRKU060XA Kintex-7：- XA7K160TVirtex UltraScale+ HBM（-3 速度级）：- XCVU31P、XCVU33P、XCVU35P、XCVU37PVivado基于命令行的 Web 安装程序增强的 VHDL2008 综合构造支持第三方电路板的集成型 GitHub 下载拥塞指标、改进的 QOR 建议，以及一般性 SSI QOR 改进增强的调试功能：IBERT GTM、RF 分析仪、HBM 监控器及总线图查看IP 子系统／内核最新 50G RS-FEC（544、514）：用于 5G 无线应用的最新 FEC (2x26G) NRZ，在添加外部 bitmux 芯片时，可实现 PAM-4 应用集成型 UltraScale/UltraScale+ 100G 以太网子系统：全新可选 AXI 数据总线接口支持基于标准的接口10G/25G 以太网子系统、40G/50G 以太网子系统、集成型 UltraScale/UltraScale+ 100G 以太网子系统、USXGMII、1G/10G/25G 以太网交换子系统：通过基于所选特性创建统计逻辑，实现尺寸优化的统计计数器视频与影像 IP：视频处理内核新增对 8K30 分辨率的支持，视频混频器增加 16 层混合，而帧缓冲器则新增对 12 和 16bpc 的支持SmartConnect：提高了面积效率、特别适合小型配置和 AXILite 端点AXI Bram 控制器：改善了单拍事务处理的性能。
可配置的读取时延，适用于紧密的时间间隔。
File size: 21.4 GBVivado® Design Suite HLx Editions include Partial Reconfiguration at no additional cost with the Vivado HL Design Edition and HL System Edition.
In-warranty users can regenerate their licenses to gain access to this feature.
Partial Reconfiguration is available for Vivado WebPACK™ edition at a reduced price.
The new HLx editions supply design teams with the tools and methodology needed to leverage C-based design and optimized reuse, IP sub-system reuse, integration automation and accelerated design closure.
When coupled with the UltraFast™ High-Level Productivity Design Methodology Guide, this unique combination is proven to accelerate productivity by enabling designers to work at a high level of abstraction while facilitating design reuse.
Accelerating High Level DesignSoftware-defined IP Generation with Vivado High-Level SynthesisBlock-based IP Integration with Vivado IP IntegratorModel-based Design Integration with Model Composer and System Generator for DSPAccelerating VerificationVivado Logic SimulationIntegrated Mixed Language SimulatorIntegrated & Standalone Programming and Debug EnvironmentsAccelerate Verification by >100X with C, C++ or SystemC with Vivado HLSVerification IPAccelerating Implementation4X Faster Implementation20% Better Design DensityUp to 3-Speedgrade Performance Advantage for the low-end & mid-range and 35% Power Advantage in the high-end文件名xvd0605
