ModelSim是业界最优秀的HDL语言仿真器

它提供最友好的调试环境，是唯一的单内核支持VHDL和Verilog混合仿真的仿真器。是作FPGA/ASIC设计的RTL级和门级电路仿真的首选，它采用直接优化的编译技术、Tcl/Tk技术、和单一内核仿真技术，编译仿真速度快，编译的代码与平台无关，便于保护IP核，个性化的图形界面和用户接口，为用户加快调错提供强有力的手段。全面支持VHDL和Verilog语言的IEEE 标准，支持C/C++功能调用和调试。ModelSim专业版,具有快速的仿真性能和最先进的调试能力，全面支持UNIX(包括64位)、Linux和Windows平台。

主要特点：RTL和门级优化，本地编译结构，编译仿真速度快；单内核VHDL和Verilog混合仿真；源代码模版和助手，项目管理；集成了性能分析、波形比较、代码覆盖等功能；数据流ChaseX；Signal Spy；C和Tcl/Tk接口，C调试。是业界唯一单一内核支持VHDL、 Verilog HDL和SystemC混合仿真的仿真器

同时也支持业界最广泛的标准如Verilog 2001、SystemVerilog等，内部集成了用于C/C++，PLI/FLI和SystemC的集成C调试器。支持众多的ASIC和FPGA厂家库，可以用于FPGA和ASIC设计的RTL级和门级电路仿真。ModelSim的最新版本ModelSim6.0(2004.8.29)。

ModelSim最大的特点是其强大的调试功能：先进的数据流窗口，可以迅速追踪到产生不定或者错误状态的原因；性能分析工具帮助分析性能瓶颈，加速仿真；代码覆盖率检查确保测试的完备；多种模式的波形比较功能；先进的Signal Spy功能，可以方便地访问VHDL 或者VHDL和Verilog混合设计中的底层信号；支持加密IP；可以实现与Matlab的Simulink的联合仿真。

ModelSim分几种不同的版本：SE、PE、LE和OEM，其中SE是最高级的版本。而集成在 Actel、Atmel、Altera、Xilinx以及Lattice等FPGA厂商设计工具中的均是其OEM版本。SE版和OEM版在功能和性能方面有较大差别，比如对于大家都关心的仿真速度问题，以Xilinx公司提供的OEM版本ModelSim XE为例，对于代码少于40000行的设计，ModelSim SE 比ModelSim XE要快10倍；对于代码超过40000行的设计，ModelSim SE要比ModelSim XE快近40倍。以下列表介绍了OEM版本（以Xilinx公司提供的ModelSim XE版本为例）与ModelSim SE版本之间的差异。

ModelSim SE支持PC、UNIX和LINUX混合平台；提供全面完善以及高性能的验证功能；全面支持业界广泛的标准；Mentor Graphics公司提供业界最好的技术支持与服务。

ModelSim SE software for simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry.

Mentor Graphics was the first to combine single kernel simulator (SKS) technology with a unified debug environment for Verilog, VHDL, and SystemC. The combination of industry-leading, native SKS performance with the best integrated debug and analysis environment make ModelSim the simulator of choice for both ASIC and FPGA design. The best standards and platform support in the industry make it easy to adopt in the majority of process and tool flows.

High Performance and Capacity Mixed HDL Simulation

ModelSim combines high performance and high capacity with the code coverage and debugging capabilities required to simulate larger blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments.

The ModelSim vopt usage mode achieves industry-leading performance and capacity through very aggressive, global compile and simulation optimization algorithms of Verilog and VHDL, improving Verilog and mixed VHDL/Verilog RTL simulation performance by up to 10X. The performance mode can also improve Verilog gate-level performance by up to 4X and capacity by over 2X. ModelSim also supports very fast time-to-next simulation and effective library management while maintaining high performance with its new black box use model, known as bbox. With bbox, non-changing elements can be compiled and optimized once and reused when running a modified version of the testbench. bbox delivers dramatic throughput improvements of up to 3X when running a large suite of testcases

Effective Debug Environment

ModelSim eases the process of finding design defects with an intelligently engineered debug environment. The ModelSim debug environment efficiently displays design data for analysis and debug of all languages.

ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs. For example, the coverage viewer analyzes and annotates source code with code coverage results, including FSM state and transition, statement, expression, branch, and toggle coverage. Signal values can be annotated in the source window and viewed in the waveform viewer, easing debug navigation with hyperlinked navigation between objects and its declaration and between visited files. Race conditions, delta, and event activity can be analyzed in the list and wave windows. User-defined enumeration values can be easily defined for quicker understanding of simulation results. For improved debug productivity, ModelSim also has graphical and textual dataflow capabilities.

The ModelSim debug environment’s broad set of intuitive capabilities for Verilog, VHDL, and SystemC make it the choice for ASIC and FPGA design.

Advanced Code Coverage

The ModelSim advanced code coverage capabilities provide valuable metrics for systematic verification. All coverage information is stored in the Unified Coverage DataBase (UCDB), which is used to collect and manage all coverage information in a highly efficient database. Coverage utilities that analyze code coverage data, such as merging and test ranking, are available. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs. Code coverage metrics can be reported by instance or by design unit, providing flexibility in managing coverage data.

The coverage types supported include:

- Statement coverage: number of statements executed during a run

- Branch coverage: expressions and case statements that affect the control flow of the HDL execution

- Condition coverage: breaks down the condition on a branch into elements that make the result true or false

- Expression coverage: the same as condition coverage, but covers concurrent signal assignments instead of branch decisions

- Focused expression coverage: presents expression coverage data in a manner that accounts for each independent input to the expression in determining coverage results

- Enhanced toggle coverage: in default mode, counts low-to-high and high-to-low transitions; in extended mode, counts transitions to and from X

- Finite State Machine coverage: state and state transition coverage

ModelSim’s advanced code coverage capabilities, ease of use, and high capacity lower the barriers for leveraging this valuable verification resource.

About Mentor Graphics

Mentor Graphics is a leader in electronic design automation software. We enable companies to develop better electronic products faster and more cost-effectively. Our innovative products and solutions help engineers conquer design challenges in the increasingly complex worlds of board and chip design.

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